VHDL Verification Course

Verification is an important part of any ASIC design cycle. It's important that complex designs are simulated fully before prototypes are built, as it's difficult to find bugs in silicon and going through additional layout cycles is costly and time consuming.

VHDL is well suited for verification. This course is an introduction to VHDL verification techniques. It assumes some familiarity with VHDL.

Stefan Doll, vc3@stefanVHDL.com

Table of Contents

Basic Stimulus Generation
Testbench Structure
Definition of Terms
Writing to Files
Reading from Files
More Reading from Files
The World of Perl
SRAM modeling
Passive SRAM Model
Signal Monitors
Generating Clock and Reset Stimulus
Approaches to Test Generation
File Read Method
VHDL pre-processing Method
Test-specific Entities
Configuration controlled Test Selection
Using Transaction Logs
Using Transaction Logs II
Using Behavioural Models
Recommended Directory Structure
Test Strategy
The End


Sponsor: BIO-SMG